The present invention relates to a system for automatically drawing net diagrams including a logic diagram, a process diagram, a relational tree diagram, a layout of a printed circuit board, and in particular, to a schematic generating method of automatically generating net diagram or logic circuit diagram and a schematic generator or system using the method suitable for generating a logic diagram, a functional diagram, or a circuit diagram in which signal flows are easily traceable based on circuit parts such as circuit elements and constituent circuits and connective information about connections therebetween.
For the conventional schematic generator, various proposals have been presented. For example, articles of such proposals have been described in the JP-A-61-204775, "A Method of Generating a Logic Diagram" in the Technical Report CAS84-134 published in 1984 from the Institute or Electronics and Communication Engineers of Japan, the JP-A-60-205672, and the JP-A-60-176177.
In an ordinary schematic generator, an entire logic circuit is subdivided through a logic division such that for each subdivided portion, arrangement of diagram drawing symbols of respective circuit parts and the like are determined in the subdivided constituent circuit through an automatic placement or placement. Routings between the circuit parts are determined through an automatic routing. In another ordinary schematic generator, the circuit parts are arranged so as to be thereafter divided, thereby generating a logic circuit diagram. These methods produce a clear diagram primarily by subdividing a logic circuit diagram in an effective fashion, by employing a hierarchic representation of the logic circuit diagram, or by using properties of particular circuit parts other than the connective relationships between the circuit parts.
Moreover, conventionally, according to a method of arranging circuit parts of a logical circuit diagram in the schematic generating method, locations in which drawing symbols are allocatable are limited to positions defined by assuming a checkerboard or grid on the objective diagram. The placements are then sequentially determined beginning from an end of the diagram in a fixed direction (for example, from an output side to an input side or in a reverse direction thereto) according to the connective relationships between the drawings symbols (namely, between the circuit parts). In a procedure to decide the placements, each drawing symbol is assigned with a level (namely, a column for placement) based on the connective relationships with an input terminal (or an input port) or an output terminal (or an output port) set as a start point or an initial point. Subsequently, intersection of the routings between the drawing symbols of the previous column (level) already assigned with positions and drawing symbols to be positioned, or the total length of the routings is minimized so as to sequentially allocate the drawing symbols of the respective columns. However, the number of placements is not necessarily limited to one. Usually, a sequential position decision from the output terminal (or the input terminal) to the input terminal (or the output terminal) and a sequential position decision in the reverse direction are repeatedly executed, thereby determining a better placement in an ordinary case. This method however is considerably less advantageous as compared with a diagram manually produced by use of a computer aided system (CAD) such as a diagram editor with regard to visibility or easy understanding of the diagram. Incidentally, for information about this type of method, reference is to be made, for example, to pages 1901 to 1904 and pages 1973 to 1974 of the 30th National Conventional Record of the Information Processing Society of Japan (1st period of 1985), the JP-A-61-204775, and pages 47 to 54 of the Technical Report CAS84-134 published in 1984 from the Institute of Electronics and Communication Engineers of Japan.
According to the conventional example above, for the placements of the drawing symbols representing the respective circuit parts and routings or routing therebetween, usually, provisional placements and routings are once determined so as to correct the resultant placements or routings in view of being easy to see. This operation however is attended with a disadvantage of a low processing efficiency. Furthermore, in the procedure of allocating the drawing symbols, the parts are located in the positions of the centers of gravity in which the parts are connected with one other or the positions in which the total routing length will be minimized. In addition, in the allocate processing, the visibility of the routings to be processed later has not been taken into consideration. As a result, a produced logic circuit diagram does not have a satisfactory visibility in some cases. Moreover, the schematic generating method has been strongly dependent on a utilization purpose thereof and on characteristics and technologies of an objective circuit, namely, considerations are not given to the generalized utilization.